1. Field of the Invention
The present invention relates to electronic devices, and in particular, to integrated circuit packages.
2. Description of Related Art
An integrated circuit (IC) package includes a chip carrier and a silicon die or chip mounted in the chip carrier, such chip including an integrated circuit. The IC package provides the means to bring input/output (I/O) signals and a voltage supply in and out of the chip. Generally, there are two interconnection levels of the IC package: the chip to the chip carrier and the chip carrier to a substrate or printed circuit board (PCB). The IC package may be directly coupled to the PCB or indirectly coupled to the PCB through a socket so that the IC package is removable.
As semiconductor chips and other devices are required to perform more functions or operations in shorter periods of time, power and signal requirements for chips are increasing. High speed performance chips, operating at low voltages, have higher current and power requirements. The higher power requirements require more power and ground paths that take up more area in the chip carrier and socket, causing difficulties in delivering stable power to the chip. Additionally, the increased I/O signal requirements call for additional I/O signal paths that compete with the increased number of power and ground paths for area in the chip carrier and socket.
One difficulty with these high performance chips is the close proximity of the power paths and I/O signal paths in the IC packages and sockets, which may result in electromagnetic interference in delivering error free signaling. Another difficulty is the high inductance and resistance of the power and ground paths. For example, a fast increase in the current drawn by the processor chip may cause a drop in the power supply voltage, since the high rate of change in current is through the inductance of the chip carrier and the socket. This is referred to as a power supply voltage droop. Improving power delivery performance, e.g., reducing voltage drop, has been accomplished by placing decoupling capacitors on the top of the chip carrier surrounding the chip and by connecting them to internal power and ground distribution planes within the chip carrier.